IonQ shows scheduled qLDPC error correction could speed up logical gates by 74x

Started by SignalFlow Depot, Oct 17, 2026, 07:05 AM

Previous topic - Next topic

0 Members and 1 Guest are viewing this topic.

Topic: IonQ shows scheduled qLDPC error correction could speed up logical gates by 74x   Views(Read 40 times)

SignalFlow Depot

IonQ researchers Mark Webster and Nicolas Delfosse have published work on running qLDPC codes much faster, and Quantum Computing Report has written it up in detail. qLDPC stands for quantum low density parity check, a family of error correcting codes that can protect many logical qubits with fewer physical ones than the surface code. Their weakness has been speed, because logical measurements are usually done one after another. This paper tackles that bottleneck directly

The approach replaces those one at a time measurements with joint measurements. A linear scheduler code decides the order, and it is combined with an adapted version of IonQ's Logical Clifford Noise Reduction scheme, known as CliNR. Shor style cat states let several commuting logical measurements happen at once. The scheduler code also allows errors across those measurements to be decoded together, which is a neat bonus

The reported speedups are large. For random logical Clifford circuits, the team reports up to 74.4 times faster execution on a code called Q102 and 18.5 times on Q70. For logical Toffoli gates, which are essential for running real algorithms, the gains are 5.0 times on Q102 and 4.2 times on Q70. On generic qLDPC codes, joint measurement gives roughly 2.4 to 3 times better performance than a standard baseline

The article says these protocols have already been folded into IonQ's fault tolerant system designs. That includes its Walking Cat blueprint, which the company has framed around breaking 256 bit elliptic curve cryptography. QCR also suggests the work shifts attention towards logical execution rate and scheduling efficiency rather than raw qubit counts

One caveat is timing. The research is newly covered, but the underlying paper first appeared in July. It is also a theoretical and numerical study rather than a hardware demonstration, so the real test will come when trapped ion machines run these schedules at scale

Is logical execution rate the metric we should all be watching now? And do you think qLDPC codes will overtake the surface code in practical machines?


Gareth_11

74x is eye catching, but the Toffoli figures are more meaningful for me. Random Clifford circuits are easy to speed up compared with the gates real algorithms need. A 4 to 5 times gain on Toffolis is still very good. It would be nice to see full algorithm estimates next. Headline numbers always come from the best case

Transformer Lynx

Worth remembering the paper is from July. QCR covering it now is fine, but it is not breaking research. Have any other groups responded to it since?

I would like to know if the results have been independently checked. Good research is still good research a few months later

RogueJaguar

Cat states doing the heavy lifting is a familiar idea, going back to Shor's early fault tolerance work. Reusing it with a scheduler code on top is a clever twist. Old ideas often find new life when hardware catches up

Preparing them reliably is its own challenge, of course. Ions handle that better than most
My finishing move is closing the laptop & walking away

Related Topics (6)