Quobly tackles quantum computing's cooling bottleneck with a new cryogenic platform

[TeaAndCode72]

French silicon spin-qubit developer Quobly and cryogenic engineering firm Absolut System signed an Industrial Partnership Declaration and qualified their first joint milestone, the QCube 100-Class 3 platform, a sub-kelvin refrigeration system delivering 100 milliwatts of continuous cooling power at 500 millikelvin. The system provides integrated thermal, mechanical and radio-frequency interfaces specifically designed to operate co-packaged cryogenic control electronics alongside Quobly's spin-qubit processors, developed under the French Cryonext program

Quobly's architecture integrates control logic directly on-chip using 300mm Fully Depleted Silicon-on-Insulator wafers co-designed with STMicroelectronics, an approach that shifts the primary scaling bottleneck away from physical chip size and toward cryogenic heat dissipation instead, since packing more integrated control electronics onto a chip generates more heat that has to be removed at extremely low temperatures. Quobly Chief Engineering Officer Nicolas Daval said the goal is preventing cryogenics from becoming a limiting factor as the company's quantum computers scale

The partnership follows a four-phase roadmap covering qualification, industrialization with double the thermal dissipation capacity, next-generation cryogenic platforms, and eventual volume production, aligned with Quobly's broader Alloy quantum computer roadmap targeting up to 100,000 physical qubits between 2027 and 2029 en route to a longer term goal of a million qubits by 2032. Curious what people think about this specific framing, does treating cryogenic cooling capacity as the primary scaling bottleneck rather than raw chip fabrication represent a genuinely important shift in how the field should think about scaling limits

Quobly and Absolut System Execute Industrial Cryogenic Roadmap for Silicon Spin-Qubit Computers - Quantum Computing Reportquantumcomputingreport.com

[NatureBoyRyan65]

Shifting the bottleneck from chip size to heat dissipation is a genuinely important reframing, it means the actual limiting factor for scaling isn't how many qubits you can fit on a wafer, it's how much of that integrated electronics heat you can physically remove