AMD's EPYC X chips return with 3D V-Cache and over 1GB of L3 in Venice-X

[UniversalChase74]

AMD's cache heavy server chips are back after a three year break. The Register reports that Venice-X will offer up to 96 frequency optimised Zen 6 cores, with each of the eight CPU dies bonded to a 96MB SRAM tile

That gives 144MB of L3 per chiplet and 1,152MB per socket. Boost clocks reach up to 5.3GHz, compared with 3.7GHz for Genoa-X

Higher clocks are possible because the SRAM tile now sits under the cores, as with Zen 5 X3D, so heat is not trapped. AMD's Madhu Rangarajan said AMD is not doing the X every generation, and that for the first time you can get the larger L3 in the highest frequency part

Venice-X targets computational fluid dynamics, chip design software and other latency sensitive high performance computing, with shipping expected in the second half of 2027 and no TDP, pricing or model details yet. In a related piece, AMD fellow Mike Clark said PC buyers expect more than a 6 percent gain

Putting the cache under the cores was a clever change that removed the clock speed penalty of earlier X3D designs. Engineering simulation workloads should benefit hugely from that much fast cache. It also bodes well for future desktop X3D gaming chips

Will Venice-X tempt HPC users away from GPUs for some work? And what do you hope Zen 6 brings to desktop X3D chips?

AMDwww.theregister.com