RISC-V explained why an open chip standard matters

[David12]

TL;DR

• RISC-V is an open, royalty free instruction set architecture, the basic language a processor understands, first developed at UC Berkeley from 2010
• Anyone can build a RISC-V chip without paying licence fees, and designs can be open source or proprietary
• RISC-V is already everywhere in embedded systems: microcontrollers, storage controllers, GPU management cores, IoT chips and boards such as the Raspberry Pi Pico 2
• The RVA23 profile, ratified in October 2024, sets a common baseline for application class processors, helping operating systems and software target RISC-V reliably
• RISC-V's openness helps security research, custom accelerators including for cryptography and national technology strategies, while its software ecosystem continues to mature

What an instruction set architecture is

Every processor speaks a language called its instruction set architecture, or ISA. The ISA defines the basic operations a chip can perform, such as adding numbers, loading data from memory or jumping to another part of a program. Software is compiled into instructions from a specific ISA, which is why programs built for one kind of processor will not run on another without translation. The ISA is the contract between hardware and software

For decades, two families dominated. The x86 architecture, controlled by Intel and AMD, powers most desktop computers and servers. The Arm architecture, licensed by Arm Holdings, powers nearly every smartphone and a growing share of laptops and servers. Using either requires licences, and in Arm's case companies pay fees to design or use cores

RISC-V offers a third path. Its specifications are published openly, and anyone can implement them without paying royalties. Companies can build their own cores, buy cores from vendors or use open source designs. This openness has made RISC-V one of the most talked about developments in chip design of the past decade

Where RISC-V came from

RISC-V began in 2010 as a research project at the University of California, Berkeley, led by Krste Asanovic with graduate students Yunsup Lee and Andrew Waterman and with guidance from computer architecture pioneer David Patterson. The name reflects its roots in reduced instruction set computing, a design philosophy Patterson helped pioneer, and the fact that it was the fifth such design from Berkeley. The team wanted a clean, modern ISA free of legacy baggage and licensing restrictions for teaching and research. Industry interest followed quickly

In 2015, the RISC-V Foundation formed to steward the standard, and in 2020 it moved to Switzerland and became RISC-V International. The organisation now has thousands of members, including major chip companies, cloud providers, universities and governments. Specifications are developed through working groups and ratified by members. Neutral governance is central to RISC-V's appeal

How RISC-V is designed

RISC-V uses a small base instruction set plus optional extensions. The base integer set handles core operations, and standard extensions add features such as multiplication, floating point arithmetic, atomic operations, compressed instructions, vector processing and cryptography. Designers pick the extensions they need, making RISC-V suitable for anything from tiny microcontrollers to powerful servers. Custom extensions can be added for specialised workloads

That flexibility created a risk of fragmentation, where software written for one RISC-V chip might not run on another. Profiles address this by defining standard sets of extensions for particular classes of processor. The RVA23 profile, ratified in October 2024, sets a common baseline for application processors that run full operating systems, including mandatory vector processing and hypervisor support. Operating system vendors and software developers can target RVA23 with confidence

Where RISC-V is already used

Embedded systems are RISC-V's stronghold. Microcontrollers in appliances, sensors and industrial equipment increasingly use RISC-V cores, and companies such as Espressif ship popular Wi-Fi and Bluetooth chips built on them. The Raspberry Pi RP2350 microcontroller, launched in 2024 for the Pico 2 board, includes RISC-V cores alongside Arm cores, letting hobbyists switch between them. Storage companies use RISC-V in drive controllers

Many people use RISC-V without knowing it. NVIDIA has said it uses RISC-V cores inside its GPUs for management and control functions, shipping them in very large numbers. Other chips use RISC-V for security processors, power management and specialised accelerators. These hidden cores are where most RISC-V deployments sit today

Automotive is a growing market. Cars contain dozens of microcontrollers for everything from engine management to infotainment, and the industry values long product lifetimes and supply security. Several chip suppliers and car makers have announced RISC-V based products and joint ventures. Functional safety certification for RISC-V cores has become an active area

Space and high reliability systems are adopting it too. NASA's High Performance Spaceflight Computing processor, developed with Microchip, uses RISC-V cores from SiFive. Open, verifiable architectures appeal to mission critical applications. Long product lifetimes in space and defence also favour standards not controlled by a single company

Application processors are the next frontier. Companies are building RISC-V cores for laptops, edge servers and data centres, and Linux distributions including Debian and Ubuntu offer RISC-V versions. Debian 13, released in 2025, added 64 bit RISC-V as an official architecture. Phones and mainstream PCs remain dominated by Arm and x86 for now, largely because of software ecosystems

Why openness matters

Cost and freedom are the most obvious benefits. Without royalties, companies can experiment with custom processors and specialised accelerators more cheaply. Startups and universities can build chips without negotiating licences. That lowers barriers to innovation, much as open source software did for programming

Customisation is another advantage. Designers can add custom instructions tailored to their workloads, such as AI inference, signal processing or cryptography, while remaining compatible with the standard base. This lets companies differentiate without abandoning a shared software ecosystem. It has made RISC-V popular for domain specific accelerators

Education and research benefit enormously. Students can study, modify and build real processor designs without legal barriers, and many university courses now teach computer architecture using RISC-V. Open source cores and simulators make hands on learning accessible. A generation of engineers is growing up with the architecture

Security research benefits from transparency. Open specifications and open source cores let researchers inspect designs, test for vulnerabilities and develop new protections. Projects such as CHERI, which adds hardware memory protection capabilities, have RISC-V implementations, including the CHERIoT design for embedded devices backed by Microsoft and others. Hardware security is easier to study when designs are not secret

National strategies also play a role. Governments and companies in Europe, India, China and elsewhere see RISC-V as a way to reduce dependence on architectures controlled by a few foreign firms. The EU has funded RISC-V research for high performance and secure computing. This geopolitical dimension has made RISC-V a policy topic as well as a technical one

RISC-V and cryptography

RISC-V includes standard cryptography extensions that accelerate operations such as AES encryption and SHA hashing, ratified in 2021 for scalar processors, with vector cryptography extensions following. Custom extensions can accelerate post quantum algorithms such as ML-KEM and ML-DSA, which rely on polynomial arithmetic that benefits from specialised instructions. Researchers have published RISC-V designs with post quantum acceleration. That flexibility could help constrained devices adopt post quantum cryptography efficiently

For Q-Day watchers, this matters because many of the hardest migration problems sit in embedded systems with limited compute. A RISC-V microcontroller with post quantum acceleration could verify ML-DSA signed firmware quickly and with low power. Open designs also make it easier to verify that implementations resist side channel attacks. RISC-V is therefore part of the post quantum hardware story

Challenges

Software ecosystems take time to mature. Compilers, operating systems, libraries and applications must be ported, optimised and tested for RISC-V. Major progress has been made, with strong support in GCC, LLVM and Linux, but gaps remain for some commercial software and drivers. Developers need hardware to test on, which has historically been scarce for high performance RISC-V

Performance at the high end is still catching up. The best Arm and x86 cores benefit from decades of investment, and RISC-V application processors are only now reaching competitive levels in some segments. Several companies are working on high performance designs for servers and PCs. Real world benchmarks will determine adoption

Fragmentation remains a concern despite profiles. Custom extensions and differing implementation choices can complicate software support. Profiles such as RVA23 and compliance testing help, but discipline across the industry is needed. Healthy standards governance is crucial

Talent and tooling are catching up. Commercial development environments, debuggers and verification tools from major electronic design companies now support RISC-V. Hiring engineers with RISC-V experience has become easier as adoption grows. These ecosystem factors often matter more than raw performance

Geopolitics cuts both ways. While openness appeals to many countries, some policymakers have raised concerns about open chip technology and export controls. RISC-V International's location in Switzerland is partly intended to keep the standard neutral. How these debates evolve could affect global collaboration

What to watch

• High performance RISC-V application processors reaching laptops and servers
• Android and mainstream operating system support for RVA23 class devices
• Growth of RISC-V in automotive, where safety and long lifetimes matter
• RISC-V accelerators for AI and post quantum cryptography
• Open source secure designs such as CHERIoT moving into products
• Policy debates on open hardware and export controls

Closing thoughts

RISC-V brings the openness of open source software to the foundation of computing hardware. It is already shipping in enormous numbers inside embedded systems, and its reach is extending towards application processors and data centres. Openness supports innovation, customisation, security research and national resilience. The main challenges, software maturity and high end performance, are being tackled steadily

If you have built projects on RISC-V boards or worked with RISC-V in industry, please share your experiences below. Beginners curious about chip design are especially welcome. This is a great moment to learn about an architecture that may shape computing for decades


Key references for citation

• RISC-V International, RISC-V specifications and RVA23 profile, ratified October 2024
• Waterman, Lee, Patterson and Asanovic, The RISC-V Instruction Set Manual
• Raspberry Pi, RP2350 microcontroller announcement, August 2024
• Debian 13 release notes, 2025
• CHERIoT project documentation

[Amber99]

Switching the Pico 2 between Arm and RISC-V cores was such a neat way to learn. Same board, same peripherals, different instruction sets

It made the idea of an ISA concrete for my students. They compiled the same program for both and compared the output

Hands on beats any lecture. Highly recommend it for classrooms. The board is cheap enough for every student to have one. Our school bought a class set this year. Lessons have never been more popular

[Scholar95]

Hidden cores are an underappreciated point. People think of RISC-V as a future technology, yet billions of cores already ship inside other chips. Few consumers ever hear about them

Management and security processors are perfect fits. Nobody needs to port an operating system to them, so the software ecosystem barrier barely applies. That is why adoption there was so fast. High end processors are a different story

Application processors will take longer. But the embedded foothold gives the ecosystem money and experience

[EventHorizon]

Post quantum acceleration on RISC-V is a great angle. Embedded firmware verification with ML-DSA is going to strain small microcontrollers

Custom instructions for polynomial multiplication could make the difference between seconds and milliseconds at boot. Several academic designs show big speedups. I hope vendors turn them into products soon. Secure boot is where it matters most

[Andy92]

Is RISC-V realistic for a small hardware startup building an IoT product today? We are choosing between an Arm Cortex-M part and a RISC-V microcontroller

Price and power look similar. My worry is toolchain maturity and long term supply. Has anyone shipped a commercial product on RISC-V microcontrollers recently? Our firmware team has only used Arm before. Retraining time matters too

Real experiences would help more than spec sheets. We ship in volume next year